This invention relates to timer circuits for providing a selectable time interval, and more particularly to a low cost method and apparatus for improving the resolution of the selected time interval.
One type of timer circuit includes a ramp generator for providing the selected time interval. Ramp generator circuits are typically precision analog circuits that provide an analog ramp signal having known linear characteristics in response to an input signal. The slope of the ramp is controlled by a ramp timing control input, typically a digitally-controlled precision current source. A comparator receives the ramp signal and a reference voltage and generates an output signal when the magnitude of the ramp increases beyond the reference voltage. An example of a prior art ramp generator and a prior art comparator is taught in U.S. Pat. No. 4,843,255 ('255) to Stuebing. The ramp generator and comparator taught in the '255 patent are designed with bipolar transistors to achieve high operating speed, a wide range of ramp slopes and corresponding time intervals, and temperature stability. Since the ramp generator, including the comparator, is designed with bipolar transistors, the output of the comparator has emitter-coupled logic ("ECL") voltage levels. ECL logic levels are typically 3.5 volts for a logic low and 4.1 volts for a logic high.
Another type of timer circuit includes a counter-timer for providing the time interval. Counter-timer circuits are typically digital circuits that initiate a count of a user-selectable number of clock cycles in response to an input signal. The number of clock cycles desired is loaded into the counter via a digital bus. After the selected number of clock cycles is reached by the counter, a terminal count output signal is generated. Thus, the terminal count signal occurs after a preselected time interval equal to the number of counted clock cycles. Counter-timer circuits are manufactured by Motorola (MC74AC161), National Semiconductor (74AC161), Texas Instruments (SN74HC160), and Signetics (74HC161), among others. The counter-timer circuits listed above are designed with complementary metal-oxide-silicon ("CMOS") transistors to provide a wide range of time intervals with low power consumption, but only at lower operating speeds (time intervals not less than ten nanoseconds). The output of the counter-timer has CMOS voltage levels, typically zero volts for a logic low and five volts for a logic high.
A ramp generator circuit is capable of finely resolving a time interval. However, the accuracy of the time interval of a ramp generator circuit is a function of how accurately the slope of the ramp can be generated. The slope of the ramp can usually be maintained within a certain percentage of a nominal slope. For example, short term jitter of such an analog ramp can be on the order of .+-.1%, while DC drift over temperature can be on the order of .+-.5%. Thus, if a 1 .mu.s time interval is required, short term jitter is .+-.10 ns, and the time interval is accurate over temperature within .+-.50 ns. Correspondingly, if a 100 ns time interval is required, short term jitter is .+-.1 ns, and the time interval is accurate over temperature within .+-.5 ns. Therefore, at shorter time intervals, although the percentage of accuracy is not changed, the absolute accuracy is improved. As absolute accuracy of a timing interval improves for a faster ramp, absolute resolution or precision of the timing interval may also improve.
A counter-timer circuit can resolve a time interval within plus or minus one half of a clock cycle. The accuracy of the time interval of a simple low-cost CMOS counter-timer circuit is a function of jitter on the terminal count output signal, also plus or minus one half clock cycle. Jitter exists because the system clock coupled to the counter-timer is asynchronous with the input signal. Thus, if a 1 .mu.s time required, the time interval is accurate within plus or minus one half clock cycle, .+-.10 ns or .+-.1%, assuming a 50 MHz clock signal. Correspondingly, if a 10 .mu.s time interval is required, the time interval is still accurate within plus or minus one half clock cycle, .+-.10 ns, but this represents a relative accuracy of .+-.0.1%. Therefore, at longer time intervals, although the absolute accuracy has not changed, the percentage of accuracy is improved. One important limitation of conventional counter circuits, however, is reset time, because the counter circuit is not operational and cannot be restarted during this time. Typical counter circuits require as much as four clock cycles or 80 ns to properly reset.
Improved accuracy, resolution, and reset time can be obtained with more elaborate and expensive counter-timer circuits. For example, one type of counter-timer circuit includes an oscillator to generate an internal clock signal. The internal clock is triggered by the input signal, and therefore the input signal is synchronous with the clock signal. The resultant terminal count output signal does not exhibit jitter. However, the internal clock requires additional circuitry such as a precision high speed startable oscillator, thus greatly adding to the complexity and cost of the circuit. In addition, for time intervals not an integral number of clock cycles, resolution and accuracy are still determined by the period of the clock signal.
Another type of counter-timer circuit that improves both accuracy and resolution is an ECL counter-timer circuit. An ECL counter-timer circuit operates with clock signals approaching one gigahertz (1000 MHz). Such an extremely fast clock signal virtually eliminates jitter at most operating frequencies and greatly improves accuracy. An ECL counter-timer operating with a fast clock signal also has a shorter reset time than its CMOS counterpart. However, the enhanced performance is at the price of greatly increased circuit cost and high power consumption.
What would be desirable is a timer circuit that combines the resolution of a ramp generator and low cost of a CMOS counter-timer to provide a wide range of finely resolved and substantially accurate time intervals.